As semiconductor technology has advanced into the deep submicron regime, the core power supply voltage is scaled down in concert with the scaling of the core power domain transistor dimensions. Similarly, an input/output (I/O) power supply voltage for I/O power domains has also been scaled down. Nevertheless, input/output (I/O) standards from higher-voltage I/O power domains may still need to be supported. An integrated circuit may thus need an input receiver that can receive input signals from a first I/O power domain to produce corresponding core power domain output signals or second I/O power domain output signals. A first I/O power supply voltage for the first I/O power domain is typically significantly higher than a second I/O power supply voltage for the second I/O power domain or a core power supply voltage for the core power domain. Given the disparity between various power supply voltages, devices in the input receiver are stressed and may malfunction if the voltage difference across their terminals (gate to source, gate to drain, or drain to source) exceeds the power supply voltage for their particular power domain. The following discussion will designate the high supply voltage for the high power domain as VDDPX and designate the low power supply voltage for the low power domain as VDDIX.
Given the need for low power domain devices to accommodate the reception of high power domain input signals, a variety of low power domain input receiver architectures have been developed. For example, it is conventional to use a native low power domain pass transistor to pass input signals from the high power domain. In such receivers, the native pass transistor has its gate biased by the low power supply voltage. Thus, even though a terminal such as the drain of the native pass transistor is exposed to the high power supply voltage, the gate-to-drain voltage difference for the native pass transistor does not exceed the power supply voltage difference VDDPX-VDDIX such that the native pass transistor is not stressed despite its exposure to the high power supply voltage.
Given its zero threshold voltage, the native pass transistor passes the high power domain input signal as a low power domain input signal that cycles between ground and the low power supply voltage. However, the usage of native pass transistors suffers from a number of problems. For example, an external source drives the high power domain input signal. A input receiver designer may thus have no control over the quality of the high power domain input signal. Given this lack of control, the native pass transistor is forced to pass whatever duty cycle and slew rate it receives through to the remainder of the input receiver. The duty cycle and slew rate for the low power domain input signal passed by the native pass transistor may thus be unacceptably distorted. More fundamentally, native devices are no longer available at deep submicron process nodes. Various receiver architectures have thus been developed using non-native low power domain devices. However, these non-native receivers are subjected to the same duty cycle and slew rate distortion issues that native pass transistor approaches suffer from. In addition, the non-native devices are strained by excessively fast slew rates and also excessively slow slew rates for the high power domain input signal.
An example non-native input receiver 100 is shown in FIG. 1. In this embodiment, the high power supply voltage is 3.6V whereas the low power supply voltage is 1.8V. Thus, a high power domain input signal 102 received at an input pad 105 cycles between 0V and 3.6V. A waveform splitter 110 splits high power domain input signal 102 into an upper-half signal 125 and a lower-half signal 130. Upper-half signal 125 cycles between 1.8V and 3.6V whereas lower-half signal 130 cycles between 0V and 1.8V. A single 3.6V input receiver 115 combines upper-half signal 125 and lower-half signal 130 to produce a combined signal 140 that cycles between 0V and 3.6V. A voltage translator or step down circuit 120 translates combined signal 140 into a low power domain output signal 135 that cycles between 0V and 1.8V.
Since 3.6V input receiver 115 has to support a 3.6 volt swing in combined signal 140, it will generally require some form of gate coupling from input pad 105 to provide sufficient overdrive voltage to its devices. The slew rate for high power domain input signal 102 must thus be confined to a relatively narrow range to keep the devices in 3.6V input receiver 115 within their reliability range. Moreover, since 3.6V input receiver 115 has just a single intermediate power supply voltage of 1.8V, providing sufficient hysteresis between the processing of upper-half signal 125 and lower-half signal 130 is problematic.
Accordingly, there is a need in the art for more robust input receivers for receiving high power domain input signals using non-native low power devices.